1. Field of the Invention
The present invention is directed to an input buffer circuit, and in particular, to an improved input buffer circuit capable of automatically and precisely controlling a timing of an input signal which is to be stored in a cell.
2. Discussion of the Related Art
The constitution of a conventional input buffer circuit will now be described with reference to FIGS. 1-4.
FIG. 1 is a structure diagram illustrating the conventional input buffer circuit and its peripheral circuits. The conventional input buffer circuit 100 includes an input unit 10, a transition detecting unit 20, and a selective delay unit 30. The input unit 10 receives an input signal DIN and a write signal /WE, and outputs a first input signal DIN1. The transition detecting unit 20 detects a transition of the first input signal DIN1 and a second input signal DIN2 generated by delaying the first input signal DIN1, and outputs a detecting signal DT.sub.1. The selective delay unit 30 receives the first input signal DIN1, delays it for a predetermined time, and outputs an output signal DOUT.
The peripheral circuits of the input buffer circuit 100 include a detecting signal summing unit 102, a control signal generator 104, a writing driver 106, and a cell 108. The detecting signal summing unit 102 sums up the detecting signal DT and a plurality of detecting signals DT.sub.1, DT.sub.2, . . . , DTn which are outputted from other input units (not illustrated), and outputs a summed signal DTS having a larger pulse width than a pulse width of the detecting signal DT.sub.1. The control signal generator 104 receives the summed signal DTS, the write signal /WE and outputs a first control signal CWEN and a second control signal CIEBN. The writing driver 106 receives the output signal DOUT, and outputs a first output signal DATAB and a second output signal DATA pursuant to the first and second control signals CWEN and CIEBN. The cell 108 receives the first and second output signals DATAB and DATA.
FIG. 2 is a detailed structure diagram illustrating the conventional input buffer circuit 100.
The input unit 10 includes a NOR gate NR1 for receiving the write signal /WE and the input signal DIN, and an inverter I1 for inverting an output signal of the NOR gate NR1 and outputting the first input signal DIN1.
The transition detecting unit 20 includes an inverter I2, a delay 1, and an inverter I3 for receiving the first input signal DIN1, delaying the signal for a predetermined time, and outputting the second input signal DIN2. The transition detecting unit 20 also includes first and second transmission gates X1 and X2 for transmitting the first input signal DIN1 and an output signal of the inverter I2, pursuant to the output signal of the delay 1 and the output signal DIN2 of the inverter I3. An inverter I4 inverts transmission signals outputted from the first and second transmission gates X1 and X2, and outputs a detecting signal DT.sub.1.
The selective delay unit 30 includes delay units 2, 3, 4 for receiving the second input signal DIN2 outputted from the inverter I3, and delaying the signal DIN2. First and second switches S1 and S2 switch both terminals of delay units 2 and 3 in order to control a delay time of the second input signal DIN2. An inverter I7 is positioned between the output terminal of the delay unit 2 and a terminal of the second switch S2, and an inverter I8 is positioned between a terminal of the second switch S2 and an input terminal of the delay unit 4.
The delay unit 2 includes inverters I5 and I6 serially connected to each other, and a PMOS transistor PM1 and an NMOS transistor NM1 functioning as a capacitor between the inverters I5 and I6. The delay unit 3 has the same structure as the delay unit 2. The delay unit 4 includes a plurality of inverters I9, . . . , I9n which are serially connected.
The operation of the above-described input buffer circuit 100 will now be explained in detail.
FIGS. 3A to 3I are timing diagrams illustrating a process for an input signal to be stored in a cell by the conventional input buffer circuit 100.
When the write signal /WE illustrated in FIG. 3A is at a low level, the input unit 10 receives the input signal DIN transited from a high level to a low level, delays the input signal DIN for a predetermined time, and outputs the delayed input signal DIN1. The transition detecting unit 20 receives the delayed input signal DIN1, and outputs the detecting signal DT.sub.1 having a predetermined pulse width PW1, as illustrated in FIG. 3C, by the transmission gates X1 and X2 in the transition detecting unit 20. As mentioned before, the delay 1 and inverter I3 control the transmission gates X1 and X2.
The detecting signal summing unit 102 receives the detecting signal DT.sub.1 and other detecting signals DT.sub.1, DT.sub.2, . . . , DTn, and outputs the summed signal DTS having a pulse width PW2 larger than the pulse width PW1 of the detecting signal DT.sub.1, as illustrated in FIG. 3D.
When the control signal generator 104 receives the write signal /WE in a low level and the summed signal DTS, it outputs the second control signal CIEBN controlling the writing driver 106 by the summed signal DTS, as illustrated in FIG. 3F. On the other hand, when the control signal generator 104 receives the write signal /WE in a high level and the summed signal DTS, it outputs the first control signal CWEN by the write signal /WE in a high level, as illustrated in FIG. 3E, and does not operate the writing driver 106.
In the case that the second control signal CIEBN is in a high-level pulse width, as illustrated in FIG. 3G, when the output signal DOUT is inputted from the input buffer circuit 100 to the writing driver 106 (see FIG. 1), the output signal DOUT is stored in a cell. That is, circuit devices (not shown) provided in the writing driver receive the output signal DOUT in accordance with the high-level pulse of the second control signal CIEBN, and output the first and second output signals DATAB and DATA, respectively, as illustrated in FIGS. 3H and 3I, to the cell. As a result, the input data DIN is stored in the cell. Accordingly, when the second control signal CIEBN is in a high level, if the output signal of the buffer circuit is inputted to the writing driver, the inputted signal is stored in the cell.
The operation of the input buffer circuit 100 for controlling a timing of the output signal DOUT in order to output it to the writing driver 106 within a range of the high-level pulse width of the second control signal CIEBN will now be described.
When the input signal DIN illustrated in FIG. 4A is inputted to the selective delay unit 30 through the input unit 10 and transition detecting unit 20, the selective delay unit 30 outputs the output signal DOUT as illustrated in FIG. 4B.
If the output signal DOUT needs to be transmitted faster in order to be in the high-level pulse width of the second control signal CIEBN, both end portions of the delay unit 2 are shortened by the first switch S1. As illustrated in FIG. 4C, an output signal DS1 is outputted from the selective delaying unit 30 faster by an output time t1.
If the output signal DOUT is required to be transmitted to the writing driver 106 slower, both end portions of the delay unit 3 are connected by the second switch S2. As illustrated in FIG. 4D, an output signal DS2 is outputted from the selective delay unit 30 slower by an output time t2. Accordingly, the timing of the input signal DIN to be stored in the cell 108 can be controlled.
As discussed above, the conventional input buffer circuit 100 employs the selective delay unit 30 in order to control the timing for transmitting the input signal to the writing driver so that it can be stored in the cell 108. Here, the selective delay unit 30 includes the plurality of delay units 2, 3, 4 and the plurality of switches S1 and S2 for switching the delay units 2, 3, 4. In addition, the delay units 2 and 3 include MOS transistors functioning as a capacitor. However, the MOS transistors are easily influenced by a power supply voltage VCC, the surrounding temperatures, and other factors. Thus, the selective delay unit cannot define the delay time of the input signal precisely, making it difficult to control a timing of the input signal DIN to be stored in the cell.